1. Technical Field
Various embodiments of the present invention relate to semiconductor apparatuses. In particular, certain embodiments relate to a semiconductor apparatus having a plurality of chips that performs efficient assignment of IDs to the plurality of chips.
2. Related Art
In order to improve the degree of integration in a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of chips are stacked and packaged in a single package to increase the degree of integration, has been developed. Since the 3D semiconductor apparatus includes a plurality of chips therein, it is configured such that each chip can be distinguished by electric signals that enable the semiconductor apparatus to select a certain chip among the plurality of chips.
FIG. 1 is a view schematically illustrating the configuration of a related art semiconductor apparatus including a chip selection circuit. As can be seen from FIG. 1, three chips Chip1 to Chip3 constituting the semiconductor apparatus are stacked in a misaligned step-like shape. Each of the chips Chip1 to Chip3 respectively has chip selection pins Chip Selection Pin 1 and Chip Selection Pin 2 for receiving chip selection signals. Each of the chips Chip1 to Chip3 is respectively applied with two voltages VDD and VSS to the two chip selection pins Chip Selection Pin 1 and Chip Selection Pin 2. One of the three chips Chip1 to Chip3 may be selected based on the applied two voltages VDD and VSS applied. In the related art semiconductor apparatus, when two chip selection pins Chip Selection Pin 1 and Chip Selection Pin 2 are provided for each chip as described above, up to four chips may be selected.
However, since the chip selection pins should be additionally provided as described above in the related-art semiconductor apparatus, it is difficult to secure enough footage of the chips, and only a limited number of chips may be selected. Also, the semiconductor apparatus should be equipped with wires for connecting the voltages VDD and VSS with the chip selection pins Chip Selection Pin 1 and Chip Selection Pin 2, which makes the overall circuit wiring complicated. Further, since the chips should be stacked in a misaligned step-like shape, packaging the semiconductor apparatus is complex and difficult.
Recently a 3D semiconductor apparatus using through-silicon vias (TSVs) are being developed. The 3D semiconductor apparatus may include a plurality of chips. The plurality of chips may be electrically connected to one another through the TSVs. The semiconductor apparatus using the TSVs may be formed by stacking the chips of a same type or different types. In this regard, the semiconductor apparatus is typically formed by stacking at least one master chip and a plurality of slave chips having the same structure as the master chip. A master chip may have the same or a different structure as the slave chips.
FIG. 2 is a view schematically illustrating the structure of a semiconductor apparatus using TSVs. As shown in FIG. 2, a master chip and a plurality of slave chips may be electrically connected to one another through TSVs. The plurality of slave chips receive data signals in common which are transmitted from the master chip through the TSVs by receivers. The signals transmitted by transceivers from each slave chip are received by the master chip through the TSVs. For example, when a signal is transmitted through the TSVs, all the slave chips receive the signal, which triggers all the slave chips to operate. Accordingly, a method for selecting only a slave chip that is intended to operate is necessary. By designating a slave chip which is intended to operate, only the slave chip required to operate can receive the signal and operate, while all the slave chips receive the signal from the master chip in common.